The 80386 has two mechanisms for interrupting program execution: Exceptions are synchronous events that are the responses of the CPU to certain conditions detected during the execution of an instruction. Interrupts are asynchronous events typically triggered by external devices needing attention. INTEL 80386 PROGRAMMER'S REFERENCE MANUAL. From Computer History Wiki. Jump to: navigation, search. INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 The initial 80386 was a 32-bit chip, incorporated 275,000 transistor, was capable of performing more than five MIPS (million instructions every second). The 80386 sold for $299, and was available in clock speeds between 12 and 40 MHz. The Intel 80386SX processor was introduced in 1988 as a low cost alternative to the original 386 processor. PUSH BP MOV BP, SP XCHG BP, [BP] This code functions as the 8086/8088 PUSH SP instruction on the 80386. Shift or rotate by more than 31 bits. The 80386 masks all shift and rotate counts to the low-order five bits. Intel 80386 Reference Programmer's Manual Table of Contents Chapter 1 -- Introduction to the 80386. 1.1 Organization of This Manual; Part IV Instructions Set Chapter 17 -- 80386 Instruction Set. 17.1 Operand-Size and Address-Size Attributes; 17.2 Instruction Format. Appendices. Appendix A -- Opcode Map; 4.1.3 Control Registers. Figure 4-2 shows the format of the 80386 control registers CR0, CR2, and CR3. These registers are accessible to systems programmers only via variants of the MOV instruction, which allow them to be loaded from or stored in general registers; for example: MOV EAX, CR0 MOV CR3, EBX. 80386 instructions when they modify memory. An undefined-opcode exception results from using LOCKbefore any instruction other than: Bit test and change: BTS, BTR, BTC. Exchange: XCHG. Two-operand arithmetic and logical: ADD, ADC, SUB, SBB, AND, OR, XOR. One-operand arithmetic and logical: INC, DEC, NOT, and NEG. 80386 has a data bus of 32-bit. It holds an address bus of 32 bit. It supports physical memory addressability of 4 GB and virtual memory addressability of 64 TB. 80386 supports a variety of operating clock frequencies, which are 16 MHz, 20 MHz, 25 MHz, and 33 MHz. It offers 3 stage pipeline: fetch, decode and execute. Finally we get to use the conditions that we defined way back in Part 2. SETcc r/m8 ; d = 1 if cc is true, d = 0 if false . The SETcc family of instructions sets an 8-bit value to 0 or 1 based on a condition code. For example, SETE al sets the al register to 1 if the ZF flag is set (equal), or to 0 if it is clear. If the destination of the SETcc instruction is an 8-bit register, it is The I/O instructions that directly refer to addresses in the processor's I/O space are IN, INS, OUT, OUTS. The 80386 has the ability to selectively trap references to specific I/O addresses. The structure that enables selective trapping is the I/O Permission Bit Map in the TSS segment (see Figure 8-2 ). The I/O permission map is a bit vector. 14.8.2 Location of First Instruction The starting location is 0FFFFFFF0H (sixteen bytes from end of 32-bit address space) on the 80386 rather than 0FFFFF0H (sixteen bytes from end of 24-bit address space) as on the 80286. Many 80286 ROM initialization programs will work correctly in this new environment.